The present invention relates to a logic verification apparatus, and relates more particularly to a technique which is effective when it is applied to a logic verification technique in a desired section of a desired program.
The U.S. Pat. No. 4,937,770 issued to Samuels et al. discloses a simulation system.
In a conventional logic verification apparatus, a test program is executed and a logic verification is carried out after carrying out an alteration. Elusive DIAG (diagnosis) instructions are included in a source code of the test program which includes an initializing unit for setting an initial value and an expected value for the simulation, a testing unit for testing the simulator, and a result decision unit for providing a decision after comparing a result of the execution of the testing unit and the expected value. In the application of this test program, when one of the DIAG instructions has been detected during a period when an architecture simulator or an instruction interpreter for simulating an operation equivalent to the logic circuit model to be tested executes the initializing unit in a data transfer level, the status of an information group relating to the logic circuit structure at this time is registered in the file as an initial value, and when another DIAG instruction has been detected after executing the testing unit, the status of the logic circuit structure information at this time is registered in the file as an expected value. Then, after the initial value has been set in the logic circuit model, the circuit model executes the testing unit and the result of the execution is compared with the expected value and a decision is made. Thus, the logic verification is completed.
Regarding a logic verification for sequentially calculating output signal values of whole basic logic elements in a gate level within the circuit model, a method for achieving this logic verification by executing only a fixed test instruction sequence, that is a part of the test program, on the circuit model is disclosed in JP-A-4-291460 which corresponds to the Japanese patent application Ser. No. 07/854,394 filed on Mar. 19, 1992 by Y. Onodera et al.
In this logic verification, during an execution of a test program, for example, logic quality or a logic verification environment at the time when an interruption instruction has been detected applies a limit on the execution to the program to be executed in the circuit model. In this case, it is necessary to select and execute a portion which can be executed by the program based on the logic quality and the logic verification environment at this location. In other words, according to the prior art technique, there is a problem that it is necessary to build in advance exclusive DIAG instructions in the source program to be executed, or it is necessary to alter the program source code. There is also a problem that the logic verification cannot be applied if the source code of a benchmark program or an application program has not been changed.